ISU Electrical and Computer Engineering Archives

ROBUST DESIGN OF HIGH GAIN AMPLFIIERS USING DYNAMICAL SYSTEMS AND BIFURCATION THEORY

He, Chengming (2007) ROBUST DESIGN OF HIGH GAIN AMPLFIIERS USING DYNAMICAL SYSTEMS AND BIFURCATION THEORY. PhD thesis, Iowa State University.

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Abstract

High gain operational amplifiers are by far the most fundamental building block in analog and mixed-signal design. In the first few chapters, design of high gain CMOS positive feedback amplifiers (PFAs) is studied. A low-voltage positive feedback amplifier in standard digital CMOS with <=3 transistors stacked between VDD and VSS is designed and circuit details are discussed. With the use of a linear precision MOS voltage attenuator and a digital tuning network, the PFA was simulated to have 100dB DC gain at the operating-point and > 70dB DC gain over a 2Vpp output swing range. Test results of fabricated chips confirmed better than 90dB operating-point DC gain, 60dB DC gain over 2Vpp. It has nearly 90 degrees of phase margin and 140MHz gain-bandwidth product when driving 1pF capacitive load with 1mA from 3.5V single supply. Both linear and nonlinear behaviors of the PFA are carefully studied in order to enhance and maintain high gain automatically. Inherent nonlinearity in its DC transfer curve is discovered and analyzed. Based on nonlinear dynamic systems and bifurcation theory, we predict bifurcation and hysteresis phenomena in the PFA. An algorithm, which can be implemented using simple digital logic, is developed to measure the PFA’s open-loop stability as the bifurcation parameter changes. Parameter-tuning algorithms are constructed that systematically move the amplifier’s operational point towards the bifurcation point, at which infinite DC gain happens. In order to compensate for the PFA’s high sensitivity to process and temperature variations, flexible analog design integrating digital programmability and inexpensive and adaptive digital post-processing techniques are developed. This flexibility and post-processing capability could dramatically enhance the PFA’s yield. Full corner simulation results over wide temperature range verify the bifurcation phenomena and the effectiveness of the control algorithms. It is shown that this amplifier can maintain high performance in the most advanced digital CMOS technology at very low voltage supplies. They also demonstrate that the proposed approach offers a robust PFA design with both high yield and high performance. Matching of critical components is the most fundamental property that is necessary in achieving high linearity performance of analog mixed-signal circuits. Although matching qualities in future advanced digital CMOS technology are forecast to deteriorate as feature sizes continue to shrink, there has not been significant progress in developing advanced matching layout strategies. Chapter 4 is devoted to addressing this issue. In this chapter, systematic mismatch error in integrated circuits due to gradient effects is modeled and analyzed. Three layout strategies with improved matching performance are proposed and summarized. The hexagonal tessellation pattern can cancel quadratic gradient errors with only 3 units for each device and has high area-efficiency when extended. Both the Nth-order circular symmetry patterns and Nth-order central symmetry patterns can cancel up to Nth order gradient effects between two devices using 2N unit cells for each one. Among these three techniques, the central symmetry patterns have the best-reported matching performance for Manhattan structures; the circular-symmetry patterns have the best theoretical matching performance; and the hexagonal tessellation pattern has high density and high structural stability. The Nth-order central symmetry technique is compatible to all IC fabrication processes requiring no special design rules. Simulation results of these proposed techniques show better matching characteristics than other existing layout techniques under nonlinear gradient effects. Specifically, two pairs of P-poly resistors using 2nd and 3rd-order central symmetry patterns were fabricated and tested. Less than 0.04% mismatch and less than 0.002% mismatch were achieved for the 2nd and the 3rd-order structures, respectively. Our proposed new layout strategies improved matching performance significantly.

EPrint Type:Thesis (PhD)
Subjects:Computer Engineering > VLSI > Mixed Circuit VLSI
Electrical Engineering > SYSTEMS AND CONTROL > Adaptive & Nonlinear Control
ID Code:331
Identification Number:TR-2007-04-13
Deposited By:George He
Deposited On:30 August 2007

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