Nanocrystalline silicon thin film transistors
Panda, Durga (2006) Nanocrystalline silicon thin film transistors. PhD thesis, Iowa State University.
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Flexible, large area circuits represent a new form of electronics which have led to rapidly rising and promising applications in displays, sensors, medical devices and other areas. The most important challenge in realizing these macroelectronic systems is fabricating the required thin film transistors on plastic substrates with a low thermal budget. Here most TFTs are fabricated using amorphous silicon (a-Si) as the active channel layer and amorphous silicon nitride as the gate dielectric layer. Low device mobility and electrical instability are the main disadvantages of a-Si TFT. Laser annealed polycrystalline silicon TFTs offer much better device performance and stability, and enable integration of driver circuits in the same process as the pixelated array. However, poly-Si suffers from poor uniformity across the substrate, lower/reduced device yield, and higher process complexity. Recently, direct-deposited nanocrystalline silicon (nc-Si) has been introduced as an attractive material alternative for the TFT active layer. While high electron mobility (~50cm2/V-s) has been achieved in n-channel devices, the hole mobility in p-channel devices has been very low (~ 0.01cm2/V-s) and thus unsuitable for CMOS applications. In this thesis, we will describe the growth and properties of p-channel nc-Si thin film transistor (TFT) devices. In contrast to previous work, a significant improvement in the hole mobility was achieved by an innovative approach of depositing nc-Si for the channel material using very high hydrogen dilution and low ion bombardment in a PECVD reactor. The doping of the body was changed by doping with ppm levels of phosphorous, and the threshold voltage was found to change systematically as phosphorus content increased. We were thus able to show that a high-quality nanocrystalline silicon material can be controllably doped in small amounts. The TFT devices are of the bottom-gate type, grown on oxidized Si wafers. Source and drain contacts were provided by using either plasma grown p type nanocrystalline layers, or by the simple process of Al diffusion. A top layer of plasma-deposited silicon dioxide was found to decrease the off current significantly. High ON/OFF current ratios exceeding 106 were obtained. Hole mobilities in the devices were consistently good, with the best mobility being in the range of ~1.6 cm2/V-s, which is the highest so far to the best of our knowledge.
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