ISU Electrical and Computer Engineering Archives

TLB Preloading for Java applications

Gharaibeh, Bashar and Chang, J. Morris (2006) TLB Preloading for Java applications. Masters thesis, Iowa State University.

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Abstract

The increasing memory requirement for today's applications is causing more stress for the memory system. This side effect puts pressure into available caches, and specifically the TLB cache. TLB misses are responsible for a considerable ratio of the total memory latency, since an average of 10% of execution time is wasted on miss penalties. Java applications are not in a better position. Their attractive features increase the memory footprint. Generally, Java applications TLB miss rate tends to be multiples of miss rate for non-java applications. The high miss rate will cause the application to loose valuable execution time. Our experiments show that on average, miss penalty can constitute about 24% of execution time. Several hardware modifications were suggested to reduce TLB misses for general applications. However, to the best of our knowledge, there have been no similar efforts for java applications. Here we propose a software-based prediction model that relies on information available to the virtual machine. The model uses the write barrier operation to predict TLB misses with an average 41% accuracy rate.

EPrint Type:Thesis (Masters)
Subjects:Computer Engineering > COMPUTER SYSTEMS ARCHITECTURE > Computer Architecture
ID Code:265
Identification Number:TR-2006-07-4
Deposited By:Bashar Gharaibeh
Deposited On:20 July 2006

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