ISU Electrical and Computer Engineering Archives

Yield and performance enhancement of analog and mixed signal circuits

Lin, Yu (2006) Yield and performance enhancement of analog and mixed signal circuits. PhD thesis, Iowa State University.

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Parametric yield models for widely used area allocation schemes in ratio-critical analog circuits are developed in this dissertation. It is shown that some of the most widely used area allocation schemes are suboptimal and that significant improvements in parametric yield can be achieved with less intuitive area allocation approaches such as the optimal and near-optimal area allocation methods introduced in this work. Simulations and experimental results are presented which show quantitatively what improvements in yield can be achieved with improved area allocation strategies for resistive feedback amplifiers and R-2R DACs. A strategy to optimize the power consumption in a class of digitally calibrated pipelined ADCs with a kT/C noise constraint is proposed. This optimization is based upon making tradeoffs between the kT/C noise budgeted in each stage, the number of stages, and the number of comparators in each stage. It is shown that significant reductions in total power consumption can be achieved with optimal noise distribution and bit/stage allocation. Existing approaches for the design of interstage switched-capacitor amplifiers used in pipelined data converters have evolved following the notion that there are firm limits on input range and output range of the amplifier. In this dissertation, in contrast to existing approaches where the amplifier may be under-designed or over-designed in an attempt to meet a fixed signal swing window requirement, a method that enables the designer to select signal swing windows to provide acceptable levels of distortion is introduced. Following this approach, a new over-range protection scheme is developed which ensures that all residues of a given stage are mapped back into an acceptable distortion window of the following stages.

EPrint Type:Thesis (PhD)
Subjects:Computer Engineering > VLSI > Mixed Circuit VLSI
ID Code:244
Identification Number:TR-2006-04-21
Deposited By:Ms. Yu Lin
Deposited On:22 April 2006

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