Control Caching: A fault-tolerant architecture for SEU mitigation in microprocessor control logic

Ganesh, T.S. (2006) Control Caching: A fault-tolerant architecture for SEU mitigation in microprocessor control logic. Masters thesis, Iowa State University.

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EPrint Type:	Thesis (Masters)
Subjects:	Computer Engineering > COMPUTER SYSTEMS ARCHITECTURE > Fault Tolerant Systems Computer Engineering > VLSI > Digital VLSI Computer Engineering > COMPUTER SYSTEMS ARCHITECTURE > Computer Architecture
ID Code:	229
Identification Number:	Identification Number UNSPECIFIED
Deposited By:	Mr Ganesh Subramanian
Deposited On:	16 April 2006

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