ISU Electrical and Computer Engineering Archives

Design of a digital signal processing system on chip for an eddy current probe

Reed, B.J. (2006) Design of a digital signal processing system on chip for an eddy current probe. Masters thesis, Iowa State University.

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In 1965 Gordon Moore, co-founder of Intel, observed that the number of transistors per square inch on integrated circuits had doubled every year since the integrated circuit was invented. Moore predicted that this trend would continue for the foreseeable future. In subsequent years, the pace slowed down, but data density has doubled approximately every 18 months, which is the current definition of Moore's Law. The Semiconductor Industry Association roadmap derived from Moore's Law promotes continuation of the decrease in minimum feature size and wafer size increase as the bases for the semiconductor industry’s successful future. This continuation of the decrease in minimum feature size and increase in wafer size has a number of important implications. One such important implication is that there will be an increase in chip manufacturing cost. This increase in die manufacturing cost has caused chip designers to investigate the implementation of single chip systems instead of the traditional design of multiple chip systems. The benefit of having a single chip system is that it can provide the same performance yet consume less space and power than multiple chip systems, which in turn cut manufacturing cost. The research conducted describes the design and implementation of an integrated circuit digital signal processing system for an eddy current probe. For this project a digital signal processing system that removes noisy signal components and amplifies the signal produced by an eddy current probe was designed. The purpose of this system is to have the ability to detect cracks in a material and to output that information to an ADC, which then is used to provide digital information to a computer for interpolation. In order to create a digital signal processing system capable of this, multiple building blocks are needed. This includes the design of a low pass filter, a variable gain amplifier which incorporates an operational amplifier and digital-to-analog converter, a current bias cell, and a shift register. An analysis and discussion of the design and fabricated integrated circuit in a TSMC 0.18 micron process is presented.

EPrint Type:Thesis (Masters)
Subjects:Electrical Engineering > ELECTROMAGNETICS & NONDESTRUCTIVE EVALUATION > Signal Processing Applications
Electrical Engineering > MICROELECTRONICS & PHOTONICS > Semiconductor Materials & Devices Processing
Electrical Engineering > ELECTROMAGNETICS & NONDESTRUCTIVE EVALUATION > Nondestructive Testing
ID Code:223
Identification Number:TR-2006-04-9
Deposited By:Brian Joy / BJR Reed
Deposited On:15 April 2006

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