ISU Electrical and Computer Engineering Archives

Optimization techniques for decoding logic design in digital-to-analog converters

Kyaw, Kyaw (2005) Optimization techniques for decoding logic design in digital-to-analog converters. Masters thesis, Iowa State University.

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Abstract

High resolution and high speed digital-to-analog Converters are important building blocks in many telecommunications and digital signal processing circuits. To achieve high accuracy, thermometer-coded structures are almost always used either as a whole or part of a segmented architecture. However, the design of a binary-to-thermometer decoder at high resolutions to achieve high decoding speed is non-trivial and is often the bottleneck in the system. The advantages of having more thermometer-coded bits in the architecture are high linearity performance, relaxed matching requirements and higher yield. However, large binary-to-thermometer decoder usually takes a lot of area and suffers in decoding speed. Some practical ways to reduce both the time delay and the digital logic involve with the large decoders are discussed. A 10-bit digital-to-analog converter was designed and fabricated using multi-segmented linear-step decoding logic and experimental results are presented.

EPrint Type:Thesis (Masters)
Uncontrolled Keywords:Digital-to-analog converter, mixed signal circuit, decoder, analog circuit design, DAC
Subjects:Computer Engineering > VLSI > Mixed Circuit VLSI
ID Code:183
Identification Number:TR-2005-7-21
Deposited By:Kyaw Kyaw
Deposited On:22 July 2005

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