2.4GHz CMOS direct downconversion receiver front-end and VCO design
Long, Jie (2004) 2.4GHz CMOS direct downconversion receiver front-end and VCO design. PhD thesis, Iowa State University.
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The explosive growth of today’s wireless communication market has brought an increasing demand for high performance radio-frequency (RF) circuits in low-cost technologies. Because of advancements in RF CMOS circuits, devices, and passive elements in the last decade, it has become possible to develop a RF system-on-chip (SoC) that integrates RF, analog and digital circuits completely. Direct downconversion, or zero-IF downconversion architecture, shows an advantage over traditional superheterodyne architectures, because it eliminates the image rejection filter and IF filter, and employs only one local oscillator (LO), which reduces the receiver size and power dissipation significantly. For this reason, direct downconversion has drawn more and more attention recently in various wireless applications. However, direct downconversion also presents some design challenges like flicker noise, DC osets, even-order distortion, and I/Q mismatches. In this work, a thorough noise analysis and a comprehensive study of the noise mechanism of the low noise amplifier of CMOS direct downconversion receivers(DCR) is given. Also addressed is the design of a cross-coupled LC voltage-controlled oscillator (VCO). For the low noise amplifier, which presents major noise contribution to the downconversion receiver front-end, an optimization technique which employs both a parallel capacitance and an interstage inductor is proposed. The addition of this capacitance helps keep the active device relatively small, and the analysis on the eects of the interstage inductor shows that it helps boost gain of the LNA at the desired operation frequency of 2.4GHz, and oers a lower noise figure. In order to achieve direct downconversion, both a passive switching mixer and an active double-balanced mixer are presented. The passive switching mixer helps solve the problem of flicker noise, but suers power loss, while the double-balanced architecture helps relieve the problems of DC offset and second-order distortion. The last part of this presentation is about a partially tunable CMOS LC-VCO which achieves good phase noise performance at the cost of smaller tuning range. It uses on-chip spiral inductors and junction varactors in the resonant LC-tank. The presented building blocks can be used for a low-power, low-voltage DCR front-end for 802.11b/g applications. It is concluded that direct downconversion architecture can find its use in low-power, low-cost 802.11b and Bluetooth applications should the circuit design make use of the optimization techniques addressed in this work.
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