Design of a 5-GHz two-stage cascode CMOS low noise amplifier
Tanadi, Rius (2004) Design of a 5-GHz two-stage cascode CMOS low noise amplifier. Masters thesis, Iowa State University.
Full text available as:
As the popularity of wireless communication in 2.4-GHz band grows, it causes excessive occupancy by users in that band. Since it is an unregulated frequency, the 2.4-GHz band also suffers from enormous interference effects generated by devices like microwave ovens that will cause problems in wireless local area networks (WLANs). On the other hand, the 5-GHz band provides lots of unlicensed spectrum and it has less interference. Recently, much research on wireless transceivers has been focused on the 5-GHz standard. The high demand of technology in the wireless transceivers has motivated us to study the feasibility of current CMOS technology for the implementation of radio-frequency (RF) and microwave circuits. The advance in the CMOS technology has become attractive due to the possibility of integrating the whole system on a single chip. The rapid progress of scaled CMOS technology has put standard CMOS processes in a favorable role in RF circuit fabrication. This project focused on designing a 5-GHz two-stage cascode CMOS low noise amplifier (LNA) using a standard 0.18 µm fabrication process. The LNA employed inductive source degeneration topology with on-chip passive spiral inductors. An intermediate inductor is used to increase the overall gain and to decrease the noise figure. The extracted simulation results show that CMOS technology has the capability to achieve a 5-GHz LNA. The LNA draws a 7.2 mW power on a 1.8V power supply while achieves a power gain of 21 dB and noise figure of 1.54 dB. Since inductors are crucial in the design of LNA, different sizes on-chip passive spiral inductors were also designed and characterized. The LNA and inductors are fabricated using free fabrication service provided by MOSIS for educational program.
Archive Staff Only: edit this record