Multipath feedforward compensated amplifier, related dipole (doublet) compression technique, and other topics
Schlarmann, Mark E. (2004) Multipath feedforward compensated amplifier, related dipole (doublet) compression technique, and other topics. PhD thesis, Iowa State University.
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In order to truly realize entire mixed-signal systems on a chip and leverage the benefits of advanced process technologies, new low-voltage compatible amplifier topologies need to be developed. In this context, a multipath-compensated multistage amplifier is introduced. These structures are compatible with low-voltage supplies because they use horizontal techniques (cascading) rather than vertical techniques (device stacking) to achieve large DC gains. When properly designed, these amplifiers are inherently first-order and do not suffer a reduction in the achievable gain-bandwidth product due to the process of compensation. The technique relies upon pole-zero cancellation for proper operation. Absent techniques that ensure accurate cancellations, these architectures are not practical for high-speed applications. This is due to the fact that imperfect cancellations result in the appearance of slow settling components in the transient response. To overcome this problem, structures that inherently ensure accurate cancellation or those that tune themselves to compensate for variations need to be developed. A tuning strategy for a two-stage multipath-compensated amplifier was developed. It is based upon the observation that if the low-frequency pole leads the zero, the step-response is underdamped. Conversely, if the zero leads the pole, it is overdamped. By sensing the slope of the transient step response after a delay, the relationship between the location of the pole and the zero can be determined. Utilizing this information, a bias current is adjusted to modify the pole’s location relative to the zero. The process is repeated many times driving the mismatch down to an acceptable level. The concept was experimentally verified using a prototype fabricated in a 0.25 micron CMOS process. The insight gained in developing a tuning strategy for the two-stage amplifier has led to a methodology for tuning an amplifier with three or more stages. Preliminary simulations predict the technique is viable. The thesis covers two additional topics as well. The first is a new CAD tool that enables designers to quickly understand the available design tradeoffs by interactive design space exploration. The second topic is a new transresistor circuit whose linearity is comparable to existing transresistors yet offers realizations that are simpler and more compact.
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